The present invention relates to a wiring layout technique for semiconductor memory devices, and more particularly to a technique effectively applicable to attempts at reducing parasitic capacitances formed between bit lines for reading signals out of memory cells and a signal transmission line arranged on a layer above them.
Japanese Unexamined Patent Publication No. Hei 7(1995)-58215 (corresponding U.S. Pat. No. 5,625,234) discloses a wiring method for dynamic random access memories (DRAMs) (method of arranging bit lines and Y select lines).
Usually, a DRAM uses a wiring system by which Y select lines for selecting column addresses are arranged on a layer above bit lines and extend in parallel to the bit lines. However, as this wiring system entails large parasitic capacitances between the Y select lines and the bit lines, any variation in potential on the Y select lines would work in an unbalanced way on bit line pairs (bit line/complement bit line), and might destabilize the sensing of stored information from memory cells.
In view of this problem, according to the above cited patent application, Y select lines are arranged at equal distances to bit line pairs to equalize the parasitic capacitances of the bit line pairs against the Y select lines and thereby to reduce the adverse effect on the bit lines. In this wiring structure, as parasitic capacitances between Y select lines and nearby bit line pairs are balanced, sensing of stored information from memory cells can be accomplished steadily and reliably. However, even where this wiring structure is used, there is an undeniable imbalance of parasitic capacitances for other bit lines adjoining the noted bit lines. Therefore, for such adjoining bit lines, the parasitic capacitances against Y select lines are substantially equalized by twisting the bit line pairs midway on the Y select lines. Regarding the configuration of bit lines, reference may be made to Japanese Unexamined Patent Publication No. Sho 64(1989)-14954, Japanese Unexamined Patent Publication No. Hei 10(1998)-289987 (corresponding U.S. Pat. No. 6,088,283), Japanese Unexamined Patent Publication No. Hei 7(1995)-45722 and Japanese Unexamined Patent Publication No. Hei 5(1993)-218348 (corresponding U.S. Pat. No. 5,170,243 and U.S. Pat. No. 5,292,678).